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  • 9/23/2024
Welcome to Practical Exercise 02! In this session, we will guide you through the process of building a Half Subtractor using Xilinx ISE and VHDL. This exercise is perfect for those looking to gain hands-on experience with digital design and VHDL programming.

This video covers -

Introduction to Half Subtractors:
* Concept: Understand the basics of a Half Subtractor and its role in digital circuits.
* Operation: Learn how a Half Subtractor performs subtraction on two binary bits.

Project Creation: How to create a new project in Xilinx ISE for VHDL design.

VHDL Coding:
* Writing the Code: Detailed guide on writing VHDL code for a Half Subtractor.
* Explanation: Breakdown of the VHDL code and its components.

Simulation and Testing:
* Test Bench Creation: Learn how to create a test bench to simulate the Half Subtractor.
* Running Simulations: Instructions on how to run simulations and verify the design.

Synthesis and Implementation:
* Synthesizing the Design: Steps to synthesize your VHDL code using Xilinx ISE.
* Implementation: How to implement the design on an FPGA board.

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#HalfSubtractor #XilinxISE #VHDL #DigitalDesign #FPGATutorial #VHDLProgramming #DigitalCircuits #VHDLSimulation #FPGAImplementation #TechTutorial #BinarySubtraction #DigitalLogic #LearnVHDL #XilinxTools #BeginnerVHDL #PracticalExercise
Transcript
00:00Hi, this is Practical Exercise 2.
00:07Today we will design a half subtractor using VHDL and review our designs.
00:12So these are the topics we would be covering today.
00:14We are covering from the basics.
00:16So if you are familiar with some topics, you can jump to next part of this video.
00:20First we will quickly understand the half subtractor and its requirement.
00:24Then we will create a truth table and then based on that we will define the expression
00:28for half subtractor.
00:31Then we will code our VHDL design using expression which we created.
00:35Then we will quickly simulate and synthesize our design.
00:38Next we will define our behavior of our half subtractor in VHDL.
00:42Then we will simulate half subtractor behavior.
00:45Next we will review synthesized result and we will see tool generated schematic for half
00:49subtractor.
00:51Next we will review synthesized design and we will see tool generated schematic for half
00:55subtractor.
00:57First we will quick compare both the simulation results and synthesized results.
01:01So let's start.
01:02So this is our half subtractor module.
01:04So we will have two binary inputs.
01:06Input A and input B and at the output we should get difference of both the inputs and borrow
01:12as second output.
01:14First step is to create the relation between output and input for all the possible values
01:18of input A and input B. So there are two binary inputs means four possible combinations.
01:24So when both the inputs have same value then difference will be 0 and borrow will be 0
01:30too.
01:31Right?
01:32Means first and fourth set of input.
01:33Now second set when A is 0 and B is 1.
01:37Difference is very clear that is 1 but A is lower value.
01:41So to subtract here we need to borrow 1.
01:43So the borrow output is 1.
01:46Next check third set where A is 1 and B is 0.
01:50Again difference is 1 here but now A is higher value.
01:53So no borrow means borrow output will be 0.
01:56So this is our truth table for half subtractor.
01:59Now write the expression for this design.
02:01So first is difference and output is 0, 1, 1, 0 for the respective inputs and we know
02:08this is simple XOR gate.
02:10So difference is A XOR B. Now borrow.
02:13So this output do not fit straight with any basic digital gates.
02:17So this means you actually need to create expression for this.
02:21Try this.
02:22What if you invert the value of input A using a NOT gate and then use AND gate with this
02:27inverted signal and input B. So invert input A. So signal S is 1, 1, 0, 0.
02:34Now use AND gate between this and B input.
02:38So 0 and 1 is 0, 1 and 1 is 1, 0 and 0 is 0, 1 and 0 is 0.
02:46So this matches our requirement.
02:47So we can use this expression.
02:49Looks tricky right?
02:50This was the way what designers used to do in early times of chip designing.
02:55Think about the complexities.
02:56However, there are couple of ways to get those expressions from such truth table but still
03:02that was painful and time taking.
03:04And chances of errors are also high and you can assume if someone asks for little change
03:09in your design.
03:10Anyway, we do not use this approach of designing now.
03:13Luckily we have hardware description language.
03:16So we only tell that we want this output from these inputs and the tool will do all the
03:22job and design those structures and expressions for us.
03:25How easy and convenient right?
03:28So in this video, first we will write our VSDL design using the expression which we
03:32designed by our own and next we will make same design by defining the behavior of our
03:37half subtractor and then let's tool figure out that what expression and structure it
03:42is designing for us.
03:44Then we will simulate both the design and compare if we see any difference or not.
03:47And finally, we will synthesize both the designs and we will see that what structure those
03:52tools design for half subtractor and if it is different from our expression or not.
03:57So let's start the practical exercise.
04:00We will use Xilinx ISC for today project.
04:03So first we will open the Xilinx ISC project navigator.
04:07It is opening now inside virtual box.
04:10We will double click on this project navigator and we will open this.
04:16It is opening.
04:19First we will create a new project.
04:22So go to files tab.
04:24Now click on new project.
04:28Give the project name.
04:30Suppose we give half subtractor 01.
04:34Click on next.
04:36We are not working on FPGA so you can select any device from here.
04:41But make sure you select VSGL as your preferred language because we are writing code in VSGL.
04:48Click on next.
04:49So this is summary of our project.
04:52Review the information and click on finish.
04:54Now it is creating project for us.
04:57Next we will create a new module.
04:59So navigate to this button and click on new source.
05:04Now select VSGL module and give the file name.
05:08Suppose we give half sub 01.
05:12Click on next.
05:15This is our entity name.
05:17This is our architecture name.
05:20Now give the port list.
05:22So A select direction in for input type signal.
05:26B direction in.
05:29DIV direction out.
05:32DIV direction out for output type signal.
05:35BORU direction out.
05:39After entering all the ports click on next.
05:43This is the summary of our VSGL module.
05:45Quickly review the information and click on finish.
05:48So this created the VSGL structure for us.
05:52Entity is already there.
05:54And VSGL architecture body is also generated.
05:57We just need to describe our design.
05:59I have already written the expression for half subtractor.
06:02So we will copy paste to save time.
06:04These are the same expression which we designed in the slides for half subtractor.
06:10So open this file.
06:12Copy the expression.
06:14And move back to project navigator.
06:16So this is our architecture body.
06:19Now paste them inside the architecture.
06:23Perfect.
06:25Now save our VSGL code.
06:27This is our VSGL module name as half-sub-01.
06:32Select this.
06:33Adjust all the windows little.
06:36Next we will check syntax.
06:38So expand the synthesize tab and click on check syntax.
06:43So syntax is ok.
06:45Next we will do simulation.
06:47So select the simulation tab from the top.
06:51This is our half-sub-01 module.
06:54Now expand design utilities.
06:57And double click on simulate behavior module.
07:02This is simulation window.
07:03You can see waveforms here.
07:05First give a restart.
07:07So click on this restart button.
07:09Now give inputs.
07:11You can force constant here.
07:13But I will prefer to give a clock.
07:15Both are ok.
07:17So select A. Right click.
07:20Select force clock.
07:21Fill the data.
07:24Click apply and click ok.
07:28Next select P. Same right click.
07:32Force clock.
07:33Fill the details.
07:37Click apply and click ok.
07:40Now run the simulation.
07:41We will run for 1 microsecond.
07:44So click on this button.
07:46It will run the simulation for the time period which you specify.
07:50Means you can change the simulation time easily if needed.
07:54Now adjust the zoom level a little.
07:56Perfect.
07:57So we can see all the values in one screen.
08:00Let's review our output.
08:02First move this yellow marker to our first instance.
08:07So here our inputs are 0 and 0.
08:11So difference is 0.
08:13And borrow is also 0.
08:16Next move marker to second instance.
08:19Now inputs are 0 and 1.
08:22So difference is 1 and borrow is 1.
08:27Next move marker to third instance.
08:30Here inputs are 1 and 0.
08:33So difference is 1 and borrow is 0.
08:37Next move marker to fourth instance.
08:40Here inputs are 1 and 1.
08:43So difference is 0 and borrow is also 0.
08:47This means our half subtractor design is good.
08:50Now we will go back to project navigator window again.
08:54OK.
08:55Select the implementation tab again from the top.
08:58Now we wanted to see the RTLC metric of our design.
09:02So expand synthesize tab and double click on view RTLC metric.
09:08It is loading.
09:10Now select the second option and click on OK.
09:14So this is our half sub 0 1 module.
09:17A and B are our two inputs.
09:20Difference and borrow are our two outputs.
09:23Double click on this module and it displays the gate level structure.
09:29Zoom out little.
09:31These are our inputs A and B.
09:34This is AND gate where A input is inverted before doing AND and we are getting the borrow
09:41output from this AND gate.
09:44Next this box is actually XOR gate.
09:47So inputs are A and B and output is connected to difference.
09:53Let's double click on this and expand this structure.
09:56So if you have ever seen XOR gate structure then you can delete this architecture.
10:03Let's create another module for half subtractor.
10:06But now we will not tell the gate structure but we will give the inputs and output relation
10:11and tool will create the gate level structure for that requirement.
10:15So again navigate to new source.
10:18Click on this button.
10:20Select VSDL module.
10:22Give some file name suppose half sub 0 2 this time.
10:28Click on next.
10:30This is our entity half sub 0 2.
10:34This is our architecture name.
10:36Now give the port list.
10:39This time I am giving the vector type signal for both input and output for ease.
10:44So type DIN, direction is IN.
10:48Now tick this box.
10:50This is indicating the vector type signal and next give the MSB and LSB.
10:57So DIN is our input which will have two signals inside.
11:01So it will be 1 down to 0.
11:04So type 1 in MSB and type 0 in LSB.
11:09Again DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN,
11:15DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN, DIN.
11:18So one output will be our difference and another will be our borrow.
11:23Now click on next.
11:25This is summary.
11:26You can review the information here and then click on finish.
11:30Now the VSDL structure is already written.
11:34Entity is already there and for the architecture description we have the save file.
11:38So we will open that and copy paste our code.
11:42So open the saved file.
11:45This is our code.
11:47Copy this.
11:48Now go back to the project navigator.
11:52Paste the code inside the architecture.
11:54Simple.
11:55So it is done now and our code is ready.
11:59Next we will save this.
12:01Now this is important step because we have two modules now inside the same project.
12:07One is half sub 0 1 and second is half sub 0 2.
12:12And because we are working on half sub 0 2 now so we need to select it as a top module.
12:17So for that right click on this module and choose set as top module.
12:24Click on yes.
12:26Now this module is our active module and now you can see the more options below.
12:31Now the steps are same.
12:33First we will check the syntax.
12:35So navigate to the synthesize and double click on check syntax.
12:41This is ok.
12:43Now select the simulation tab from the top.
12:46This is our half sub 0 2.
12:49Now go to simulate behavior module and double click here to open it.
12:56So this is our waveform window.
12:59These are inputs and outputs.
13:02First restart the simulation.
13:04So click on this restart button.
13:07This time we will force values instead giving clock.
13:11So right click on input din.
13:14Now select force constant.
13:18Note that I have selected this vector input.
13:21So we will give 2 bit data for both inputs.
13:24So give value 0 0.
13:26Then apply and ok.
13:30Now we will run this for 1 microsecond.
13:33So click on this button.
13:36Now change the values.
13:39So select din, right click, force constant, give 0 1, apply, ok.
13:49Now run again for 1 microsecond.
13:53Change the values again.
13:55So select din, right click, force constant, give 1 0, apply, ok.
14:05Now run again for 1 microsecond.
14:09Change the values final time.
14:11So select din, right click, force constant, give 1 1, apply, ok.
14:22Now run again for 1 microsecond.
14:25Let's adjust the zoom level little.
14:28This is good.
14:29We can see all the instances in one screen.
14:32Now move the yellow slider for first instance.
14:36Ok, so din is 0 0.
14:40Then dout is 0 0.
14:42Means difference is 0 and borrow is 0.
14:47Next move slider to second instance.
14:51Now din is 0 and 1.
14:54So difference is 1 and borrow is 1.
14:59Next move slider to third instance.
15:02Now din is 1 and 0.
15:06So difference is again 1 but borrow is 0.
15:11Next move slider to fourth instance.
15:14Now din is 1 and 1.
15:17So difference is 0 and borrow is also 0.
15:21So this half subtractor is also works fine, right.
15:25Now let's see the gate level structure for this.
15:29So we will go to project navigator again.
15:32Select the implementation tab from the top.
15:35Now go to the synthesize tab and double click on view RTLC metric.
15:43Select this second option here and click on OK.
15:48This is our half sub 0 2 module.
15:50Din is our input.
15:53Dout is our output.
15:55Double click on this and expand and that will return a fixed room type structure.
16:02Let's open the technology schematic now.
16:05So double click on view technology schematic.
16:08Select this second option and click on OK.
16:12So this is our module din is input which is vector for two binary inputs.
16:19Dout is output again vector type for difference and borrow.
16:25Double click on this, zoom out little.
16:29So there are two boxes.
16:31One is for difference and another is for borrow.
16:35First open the top one.
16:37So double click.
16:38This is AND gate where input A is inverted with NOT gate.
16:43And this is our borrow output, remember?
16:48Let's open the bottom one.
16:51This is our XOR gate and the output is difference.
16:55This is the same structure which we have created for our half subtractor.
17:00You can also see the truth table for this structure as well.
17:03So click on truth table and this is the relation between inputs and outputs and this is a XOR
17:09gate.
17:11You can also view the expression for this.
17:14So click on equation tab and it will display the expression for the design.
17:20Also you can see the Kmaps for this.
17:23This was one of the simplest design you can try to start practice.
17:27This is equally important so that you can familiar with the tools and its features.
17:32This is just a start.
17:33Together we will design many different type of systems and we will do the projects too.
17:38So stay tuned for the updates, like this video, comment on video and share this video.
17:44And don't forget to subscribe to learn and grow community.

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